The JPEG/MJPEG encoder IP core is a single chip solution that supports single image and video encoding for the resolutions including QVGA and VGA up to 30fps.

The encoder IP core is a vendor and device independent, and supports, not limited to, FPGAs of Xilinx, Intel (Altera), and Microsemi. Main features are:

  • Frame format VGA, QVGA.
  • Frame rate 30fps max.
  • JPEG header included.
  • User selectable three of Quantization levels.
  • Chroma Format 4:2:2.
  • Pixel data 8bits.
  • FPGA clock 48MHz max (2 times of pixel clock).
  • External memories not required.
  • Output data rate 3.5Mbyte/sec max (Depends of frame rate and quantization level).


  • Portable digital cameras.
  • Camera door bells.
  • Video surveillance cameras.

Download JPEG/MJPEG Encoder User Manual

FPGA Resource Usage

 Below are the example synthesis results for the Xilinx Spartan 6 FPGA. Please note that the IP is a vendor and device independent.

Selected Device : 6slx9tqg144-3

Slice Logic Utilization:

Number of Slice Registers:  2494 out of  11440 (21%)

Number of Slice LUTs: 1742 out of 5720 (30%)

Number used as Logic: 1723 out of  5720 (30%)

Number used as Memory: 19  out of  1440 (1%)

Number used as SRL:  19

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 3012

Number with an unused Flip Flop: 518 out of  3012 (17%)

Number with an unused LUT: 1270 out of  3012 (42%)

Number of fully used LUT-FF pairs: 1224 out of  3012 (40%)

Number of unique control sets: 112

IO Utilization:

Number of IOs: 36

Number of bonded IOBs: 35 out of  102 (34%)

Specific Feature Utilization:

Number of Block RAM/FIFO: 18  out of 32 (56%)

Number using Block RAM only: 18

Number of BUFG/BUFGCTRLs: 2 out of 16 (12%)

Number of DSP48A1s: 11 out of 16 (68%)